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1 hour 33 seconds long

Same.

Software moves so fast that its actually an anti feature. Libraries and SDKs measure lifetime support in years, but industrial hardware support *at minimum* is a decade. A lot of these new startups dont understand that established industry wont use them unless they known this shiny new system wont ve abandoned in a few years.

On the other hand, softwate devs trying to quickly make a product have something to get them going.


More reason to stick with my monitor and Kodi.

Very limited study.

A lot of datasheets are inaccessible without signing an NDA. Even if you're a VC-backed enterprise, some unnamed chip vendors will tell you to pound sand if you're less than 8 figures of annual revenue.

Worse, many recommendations in datasheets were written in the 80s, overkill for many applications, or completely wrong and won't be updated until an errata is published 6 months later. Given current workflows, I don't see how AI would help designing a PCB with an alpha chip that's doing anything remotely novel.

More to the articles point, AI designing ASICs or other Verilog/HDL defined components could be very interesting use case


> A lot of datasheets are inaccessible without signing an NDA

Only for very high-end stuff, where just designing the board around the chip needs a team of engineers.


Not necessarily true, most recently I was working with an USB 3.1 chip that anyone can buy off DigiKey, but I had to call contacts at 4 seperate companies just to get firmware to make superspeed work. We werr just too small of a fish to make the chip vender care.

This is becoming more true as a larger percentage of hardware infrastructure is occupied by the datacenter economy.


What kind of chips are you talking about? I guess most ARM SoCs and maybe RAM/ROM ICs?

My most recent experiences have been those chips, yes. Re: my point about doing novel things.

Like the ethos but how is this different than Project Ocean or the Internet Archive?

It doesnt hurt to have multiple projects, im genuinely curious.


I'm trying to find your capabilities. I.e trace and space minimums, hole to edge minimums, min annular ring, etc. Are you not at that stage yet? Will you ever publish a standard spec?


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