The convention for that distance is actually length in most semiconductor texts. The width of a transistor is the cross-cut distance across the direction of current flow.

The below might be inaccurate. It's been a while since I last took semiconductors.

Decreasing length increases speed because there's less parasitic capacitance between the gate and the current channel underneath it, so less charge needs to be pumped onto the gate to turn the mosfet on.

An npn mosfet turns on by putting a positive charge on the gate that pushes away positive holes and pulls negative electrons into the channel under the gate. This turns the channel region from a depleted region that behaves like undoped silicon which is an insulator to a region filled with negative charges like n-doped silicon that can conduct current. But to do this, you need to put charge onto the gate, The larger the area under the gate the more charge you need to put on it and the longer it takes, or in other words the parasitic capacitance increases. This parasitic capacitance is proportional to W x L, but since decreasing W (the cross-section of current flow) decreases the current going through the MOSFET when it's turned on the approach before FinFETs was to use more precise etching technologies to decrease L.

The problem with decreasing L though is when the MOSFET is off, the small distance of "undoped silicon" under the gate isn't enough to stop current from leaking past it. You could decrease this leakage by decreasing W, but then when the MOSFET is on the max current is lower and that slows down other components down the line. This on current has to go on to charge up other gates and turn on other components.

What a FinFET does is ask, instead of turning on a MOSFET channel by having the gate act on it from just one side, why not have the gate act on it from 3 sides by sticking it out of the silicon substrate and surrounding it by the gate. Now, we can have small L and small W to decrease leakage, as well as a larger on current that's equivalent to what a regular mosfet with a larger W would have.

I'm not actually sure what this would do to the parasitic capacitance I mentioned earlier, since this should increase the "width" of the channel that the gate is contacting. Maybe the 3D configuration actually ends up reducing this capacitance? 3D EM fields is a whole other beast compared to 2D, and we're also talking about nanometer scales and semiconductor materials here. But it definitely allows you to pack transistors closer together.

I always get width and length confused in this context. My incorrect mental model has been - "source is on the left and drain is on the right therefore width is the distance between those." Thanks for the clarification.

>"What a FinFET does is ask, instead of turning on a MOSFET channel by having the gate act on it from just one side, why not have the gate act on it from 3 sides by sticking it out of the silicon substrate and surrounding it by the gate"

This was a nice way of articulating this and makes good sense. Thanks.