There's been some real uptake for large consumers of embedded cores who can use it to avoid paying ARM royalties and to be able to add their own custom instructions for their specific workloads.
And in teaching. If you're going to get a sophomore to build their first 3 stage RISC pipeline or a senior their first OoO machine with register renaming then RISC-V's consistent design removes a lot of unnecessary distractions.
I assume people are using it in research too. If I were to redo my thesis on improving adder efficiency today I'd probably look at using an open source RISC-V design as a base.
I'm skeptical of RISC-V's ability to succeed as an application core like ARM's A series or modern x86. But none the less I'm bullish on it having an important future.
And in teaching. If you're going to get a sophomore to build their first 3 stage RISC pipeline or a senior their first OoO machine with register renaming then RISC-V's consistent design removes a lot of unnecessary distractions.
I assume people are using it in research too. If I were to redo my thesis on improving adder efficiency today I'd probably look at using an open source RISC-V design as a base.
I'm skeptical of RISC-V's ability to succeed as an application core like ARM's A series or modern x86. But none the less I'm bullish on it having an important future.