The RISC-V Vector code examples shown are four or five years out of date, though this doesn't change the comparison with SVE.
In the current spec the functions of VSETDCFG and SETVL have been combined. Loads and stores now explicitly give the memory element data width (which can be different to the width in the vector registers). VFMADD with four independent register operands has been replaced with two instructions with only three register operands each: VFMADD (dst = src1 * dst + src2) and VFMACC (dst = src1 * src2 + dst) to decrease the instruction encoding space needed.
In the current spec the functions of VSETDCFG and SETVL have been combined. Loads and stores now explicitly give the memory element data width (which can be different to the width in the vector registers). VFMADD with four independent register operands has been replaced with two instructions with only three register operands each: VFMADD (dst = src1 * dst + src2) and VFMACC (dst = src1 * src2 + dst) to decrease the instruction encoding space needed.