A processor design in a HDL like Verilog or VHDL is not really a "program". It is a textual representation of physical hardware configuration. Seeing it as a program is usually the the root of problems faced by amateur HDL designers.
So true. The code describes real hardware - wires, gates, registers, memory macros. And those are finite resources. The FPGA tools allocate resources and map them to specific instances on the FPGA chip. In an ASIC there are more freedom, but the chip area, number of metal layers to route signals and delay, power sets constraints. Understanding that writing something in SystemVerilog, VHDL actually allocates physical, electrical objects is very important.
It is not bit patterns stored in a memory and interpreted, executed by something as a sequence of instructions. Routing congestion for example doesn't exist as a concept in SW.
